1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of preventing data of a non-selected memory cell from being degraded.
2. Description of the Related Art
FIG. 1 shows the schematic construction of a conventional semiconductor memory device, for example, a conventional electrically data programmable nonvolatile semiconductor memory (EPROM). In FIG. 1, memory cells MCl to MCn are each formed of a nonvolatile transistor. FIG. 2 is a cross sectional view showing the construction of memory cell MCl. Source 72 and drain 73 formed of n+-type diffusion regions are formed in the surface area of p-type substrate 71, floating gate 74 is formed above that portion of the substrate which lies between the source and drain, and control gate 75 is formed above the floating gate. The film thickness of that portion of insulation film 76 which lies between substrate 71 and floating gate 74 is set to tox1 and the film thickness of that portion of insulation film 76 which lies between floating gate 74 and control gate 75 is set to tox2.
Since the EPROM is a nonvolatile memory, data programmed into memory cell MCl can be permanently stored unless all the stored data is erased by application of ultraviolet rays. In this case, the "data programming" means that electrons are injected into floating gate 74 of memory cell MCl and data of the memory cell is set to "0". That is, memory cell MCl having data of "1" is not programmed and set in the erasing state in which no electron is injected into floating gate 74. For this reason, in order to program data into the memory cell, high voltage Vpp of 12.5 V, for example, is simultaneously applied to drain 73 and control gate 75 of the memory cell which is desired to store data "0", thereby causing hot electrons to be injected into the floating gate from the channel. As a result, the threshold voltage of the programmed memory cell transistor is raised and thus data is programmed into memory cell MCl of the EPROM. The programming operation is effected by use of an exclusive-use device which is called an EPROM writer. The EPROM is mounted on a device using the EPROM after the programming operation.
In the readout mode, voltage Vcc of 5 V, for example, is applied to control gate 75 to read out data stored in memory cell MCl.
As described above, in the EPROM, the level of a voltage applied to control gate 75 when data is programmed into data storing memory cell MCl is different from that applied when data is read out from the memory cell. For example, voltage Vcc (5 V) is applied in the data readout operation, and voltage Vpp (12.5 V) is applied in the data programming operation. Therefore, it is necessary to provide a switching circuit for switching voltages Vcc and Vpp in addition to externally supplied power source voltages Vcc (5 V), Vpp (12.5 V) and Vss (0 V).
Referring to FIG. 1 again, the switching between voltages Vcc and Vpp is effected by use of voltage switching circuit 102. Switching circuit 102 is supplied with normal data readout voltage Vcc via terminal 142 and data programming high voltage Vpp via terminal 144 and selectively supplies voltage Vcc or Vpp as voltage SW according to an programming control signal (write enable signal). Voltage Vpp is also supplied to programming control section 104. Programming control section 104 includes transistor 134 whose drain and source are respectively connected to terminal 144 and column selection gate circuit 108 and programming control buffer 132 connected to receive voltage Vpp as a power source voltage is connected to a gate of the transistor 134 to control the gate voltage of transistor 134 according to programming data Din.
Column decoder 106 decodes a column address included in the input address to output the decoded result to column selection gate circuit 108. Circuit 108 includes a plurality of N-channel MOS transistors and selects memory cell MCl based on the decoded result of decoder 106. Row decoder 110 decodes a row address included in the input address to output the decoded result to row address buffer 112. Buffer 112 is supplied with voltage SW from circuit 102 as the power source voltage and supplies a voltage to control gate 75 of memory cell MCl.
The drain and source of memory cell MCl are respectively connected to bit line 120 and ground voltage terminal Vss. Bit line 120 is connected to one input terminal of sense amplifier 116 via a plurality of transistors of column selection gate circuit 108. Sense amplifier 116 senses "1" or "0" of data stored in memory cell MCl by comparing the potential of bit line 120 varying according to data stored in one of memory cells MCl selected by row decoder 110 and column decoder 106 with an input reference voltage to be described later.
Reference voltage generation circuit 122 supplies a reference voltage to sense amplifier 116. Circuit 122 includes dummy cell DC constructed by the same non-volatile transistor as memory cell MCl, dummy bit line 118 and column selection gate circuit 114 having normally turned-on transistors of the same number as the transistors series-connected in column selection gate circuit 108. The level of the reference voltage is determined by turning on dummy cell DC. In order to obtain a stable reference potential, it is necessary to design the transistor characteristics of memory cell MCl and dummy cell DC equal to each other.
With the above construction, when data is programmed into memory cell MCl, high voltage Vpp is supplied as voltage SW from power source switching circuit 102 to row address buffer circuit 112. At the same time, high voltage Vpp is supplied from programming controlling buffer 132 to the gate of programming controlling transistor 134. If the threshold voltage of transistor 134 is Vth, a voltage of (Vpp-Vth) is supplied to the drain of memory cell MCl via column selection gate circuit 108. Further, high voltage Vpp is supplied from row address buffer 112 to the control gate of memory cell MCl. As a result, current flows in the source-drain path of memory cell MCl, causing hot electrons to be injected into floating gate 74 to raise the threshold voltage of memory cell MCl. In this way, data is programmed into memory cell MCl.
When data is read out from memory cell MCl, voltage Vcc is supplied as voltage SW from power source switching circuit 102 to row address buffer 112. At this time, voltage Vcc is supplied from row address buffer 112 to the control gate of memory cell MCl, permitting a voltage corresponding to data stored in memory cell MCl to be supplied to sense amplifier 116 via column selection gate circuit 108. A reference voltage is also supplied from reference voltage generating circuit 122 to sense amplifier 116. Then, sense amplifier 116 compares the voltage supplied from memory cell MCl with that supplied from dummy cell DC and outputs the comparison result as readout data to the data line.
FIG. 3 shows the voltage-current characteristic in a case where data is written or programmed into memory cell MCl of FIG. 1. In FIG. 3, characteristic curve a shown by a solid line indicates the characteristic of memory cell MCl itself, and characteristic curve b shown by broken lines indicates the stationary characteristic of all the transistors of column selection gate circuit 108 which are connected in series with transistor 134. In this case, intersection c between characteristic curves a and b is the operation point.
As shown in FIG. 1, a large number of memory cells are connected to a single bit line in an actual EPROM and only one of the memory cells is set into a data write-in or programming state. In other words, as shown in FIG. 1, a large number of memory cells (MCl, - - - , MCn) are connected to a single bit line 120 and outputs of row address buffers 112 are respectively applied to the control gates of the memory cells. High voltage Vpp is supplied only from that one of buffers 112 which is connected to the control gate of one of memory cells MCl to MCn to be selected and reference voltages Vss of 0 V are applied from other buffers 112. For example, when memory cell MCl is selected, high voltage Vpp is applied only to control gate 75 of memory cell MCl and reference voltages Vss are applied to the control gates of other memory cells. However, as described before, a voltage of (Vpp-Vth) is applied to the drains of all the memory cells connected to the same bit line and non-selected memory cells will receive a voltage stress due application of voltage (Vpp-Vth).
When a memory cell having data previously stored therein is subjected to the above voltage stress, electrons injected into floating gate 74 are attracted towards drain 73 and finally discharged into drain 73, lowering the threshold voltage of the memory cell and degrading data stored therein. This phenomenon is called a "drain-through" phenomenon.
FIG. 4 is a characteristic diagram showing the relation between electric field EDF between the drain and floating gate of a memory cell and the ratio of variation .DELTA.Vth in the threshold voltage to initial threshold voltage Vth with application time of the voltage stress being used as a parameter. As shown in FIG. 4, as the drain voltage becomes higher and the intensity of electric field EDF between the drain and floating gate becomes higher, or as stress application time becomes longer, then a larger amount of electrons may be emitted, increasing variation .DELTA.Vth in the threshold voltage. Therefore, in order to suppress the "drain-through" phenomenon, it is necessary to reduce the stress application time or suppress the electric field between the drain and floating gate of the non-selected memory cell. However, since the stress application time is determined by the product (n.multidot.Tpw) of data programming time Tpw for each memory cell and the number n of memory cells connected to the same bit line, there is a limit in reducing the time. On the other hand, in order to suppress the electric field between the drain and floating gate of the memory cell, film thickness tox1 of insulation film 76 in FIG. 2 may be increased to separate drain 73 from floating gate 74 by a longer distance. However, if film thickness tox1 of the insulation film is increased, the conductance of the memory cell in the read mode is reduced, lowering the data readout speed and making the write-in or programming time longer.
As described above, the readout speed and write-in or programming speed may be lowered when an attempt is made to prevent data of non-selected memory cells from being deteriorated by the voltage stress applied to the non-selected memory cells which are not selected in the data write-in or programming mode.